Asynchronous circuit synthesis with Boolean satisfiability

Asynchronous circuits are widely used in many real time applications such as digital communication and computer systems. The design of complex asynchronous circuits is a diicult and error-prone task. An adequate synthesis method will signiicantly simplify the design and reduce errors. In this paper, we present a general and eecient partitioning approach to the synthesis of asynchronous circuits from general Signal Transition Graph (STG) speciications. The method partitions a large signal transition graph into smaller and manageable subgraphs which signiicantly reduces the complexity of asynchronous circuit synthesis. Experimental results of our partitioning approach with large number of practical industrial asynchronous circuit benchmarks are presented. They show that, compared to the existing asynchronous circuit synthesis techniques, this partitioning approach achieves many orders of magnitude of performance improvements in terms of computing time, in addition to the reduced circuit implementation area. This lends itself well to practical asynchronous circuit synthesis from general STG speciications.